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| author | JF <jf@codingfield.com> | 2020-06-27 16:10:17 +0200 |
|---|---|---|
| committer | JF <jf@codingfield.com> | 2020-06-27 16:10:17 +0200 |
| commit | f8ffb405a23e02efd3b791730a3eb349e1d7efe4 (patch) | |
| tree | 4b42e3c57dcd36229530c1f9faeadf3ca10d2781 /src/FreeRTOS/portmacro_cmsis.h | |
| parent | e86991284fe5a41b913004f08f476aeeb83a71ef (diff) | |
| parent | 3dfba0b90d8549d17a2aa4d228f31fbdcf803e70 (diff) | |
Merge branch 'nimble_1_3_0' into develop
Diffstat (limited to 'src/FreeRTOS/portmacro_cmsis.h')
| -rw-r--r-- | src/FreeRTOS/portmacro_cmsis.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/FreeRTOS/portmacro_cmsis.h b/src/FreeRTOS/portmacro_cmsis.h index 3d2dee5c..0497538f 100644 --- a/src/FreeRTOS/portmacro_cmsis.h +++ b/src/FreeRTOS/portmacro_cmsis.h @@ -106,8 +106,8 @@ extern void vPortEnterCritical( void ); extern void vPortExitCritical( void ); #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortRaiseBASEPRI() #define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortSetBASEPRI(x) -#define portDISABLE_INTERRUPTS() vPortRaiseBASEPRI() -#define portENABLE_INTERRUPTS() vPortSetBASEPRI(0) +#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" ) +#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" ) #define portENTER_CRITICAL() vPortEnterCritical() #define portEXIT_CRITICAL() vPortExitCritical() |